In MOS IC formation techniques, progress has been made such that the size of unit cells of MOS devices has been reduced by 10% annually. Accordingly, the size of MOS devices (such as gate length, Lg) has been reduced from micron scale (Lg.ltoreq.1.0 .mu.m) to sub-micron scale (Lg.ltoreq.0.35 .mu.m) for increasing the density and for improving the performance of the IC.
As the size of the device is reduced to the sub-micron scale, it has become difficult to optimize the short channel effect, punch-through voltage, series resistance, current driving capability, hot carrier characteristics and the like. Accordingly, studies have been made in an attempt to improve the above factors. Particularly, of the many different characteristics of the sub-micron scale device, it is the most difficult problem to simultaneously satisfy the short channel effect and the hot carrier characteristics. Many techniques for solving this problem have been developed and reported.
As a shallow junction formation technique for reducing the short channel effect, studies have been made on silicide and RTP (rapid thermal processing). Further, studies are being conducted with respect to source/drain structures in which the source/drain region is formed with a level higher than that of the gate. This elevated source/drain structure which is formed higher than the gate includes: a recessed gate structure in which the gate is formed by recessing a silicon substrate; a polysilicon source/drain structure in which polysilicon is selectively grown on the source/drain region, and then a doping is carried out to form a shallow junction; and an epitaxial source/drain structure in which a monocrystalline silicon is selectively grown on the source/drain region instead of polysilicon. The above structures are selected depending on the process employed.
The problems of these structures are as follows. That is, in the case of the recessed gate structure, the length of the gate has a three-dimensional form, and, therefore, the gate has a sufficiently long channel, so that the characteristics would be superior viewed from the short channel effect. However, the integrity of the oxide layer near the corner of the recessed gate is low. Further, the current driving capability is lowered due to the increase of the channel length.
In the case of the polysilicon source/drain structure, the dopant is diffused from the polysilicon to the silicon substrate so as to form a shallow junction. Therefore, the drain region on the substrate is completely depleted under a high voltage, and, therefore, the end portion of the depleted junction is contacted to the polysilicon layer, with the result that a large leakage current is generated.
In the case of the epitaxial source/drain structure, a monocrystalline source/drain region is formed through selective epitaxial growth instead of using polysilicon in elevating the source/drain region as in the case of the polysilicon source/drain structure, thereby solving the problem of the leakage current. However, both the polysilicon source/drain structure and the epitaxial source/drain structure have junctions on a level deeper than the gates, and, therefore, the hot carrier problem remains as in the case of the conventional LDD structure. Further, in the case of the epitaxial source/drain, the technique of selectively growing the epitaxial layer has not yet been matured, and a high temperature is required, with the result that it is difficult to control the depth of the shallow junction.
The above conventional techniques will be described in detail referring to the drawings.
As the size of the transistor is reduced, if a high electric field is imposed between the source and drain of the transistor, the carriers (electrons) introduced from the source are highly accelerated to become hot carriers, thereby introducing a problem. When the device is progressed to a sub-micron scale, this problem is further worsened. In order to solve this problem, a process for forming the drain in the form of an LDD (lightly doped drain) was reported in "Electron Device Letter" (1980 IEEE, ED-27, p. 1359).
As illustrated in FIG. 1, this process is carried out in the following manner. That is, gate 12 is formed upon silicon substrate 11, and an ion implantation is carried out in a small amount. A CVD SiO.sub.2 is uniformly coated, and a side wall spacer is formed on the side walls of the gate by carrying out an RIE (reactive ion etching). An ion implantation is carried out to form a source/drain region in the conventional manner, and a heat treatment is carried out, thereby forming source 13 and drain 14 with LDD region 15 formed thereon. Thus, the formation of the device is completed.
However, when a device of less than half micron scale is required, the short channel effect problem newly appears besides the hot carrier problem. In order to give a solution to this problem, a process for formation of a recessed gate structure was reported in "Technical Digest" (1988 IEDM, p. 226), and according to this process, a recess is made by etching a silicon substrate, and a gate is formed in the recess. Further, a polysilicon source/drain structure was reported in "Electron Device Letter" (1986 IEEE, EDL-7, p. 314), and an epitaxial source/drain structure was reported in "Electron Device Letter" (1990 IEEE, EDL-11, p. 365), in which a monocrystalline source/drain region is formed by growing an epitaxial layer instead of the polysilicon.
As illustrated in FIG. 2, the process for formation of a device having a recessed gate is carried out in the following manner. First, lightly doped drain junction 22 is formed on silicon substrate 21. Then, this portion of silicon substrate 21 is trench-etched, and a doping is carried out to form doped channel region 23. Gate oxide layer 24 is formed, and gate 25 is formed using polysilicon, thereby completing the formation of the device.
As illustrated in FIG. 3, the process for formation of a device having a polysilicon gate is carried out in the following manner. First, gate 32 is formed on silicon substrate 31, and polysilicon layer 33 is selectively deposited on the source/drain regions, so that the dopant may be diffused from polysilicon layer 33 to the substrate, thereby forming junctions 34.
Finally, the process for formation of the epitaxial source/drain structure is carried out in the following manner. First, as illustrated in FIG. 4, gate 42 is formed on substrate 41, and LDD region 43 is formed. Side wall 44 is formed, and epitaxial monocrystalline layer 45 is selectively grown. A doping is carried out, thereby completing the formation of the transistor.
As already mentioned above, in the case of the recessed gate structure, the integrity of the gate oxide layer is worsened. Further, due to the increase in the length of the channel, and due to the consequent increase of the resistance of the long channel between the source and drain, the current driving capability is lowered.
In the case of the device having the polysilicon source/drain structure, because of the shallow junction which is formed through the diffusion of the dopant from the polysilicon to the substrate, the drain region is completely depleted under a high drain voltage. Consequently, the depleted edge of the junction is contacted with the polysilicon layer, thereby producing a large amount of leakage current.
Meanwhile, in the case of the epitaxial source/drain structure in which an epitaxially grown silicon layer is utilized, the leakage current problem can be solved. However, as in the case of the polysilicon source/drain structure, the junction is formed on a level deeper than the gate, and therefore, the hot carrier problem occurs as in the case of the conventional LDD structure.